ASIC/FPGA Conversions

Tekmos can convert your FPGA design into an ASIC. Working from your design files, we can generate a pin-compatible ASIC with lower cost and continued availability.

How It Works

Starting from either your netlist or your binary bitstream data, Tekmos translates your design into our own library. We evaluate the design's timing, run simulations if available, and add scan if necessary. We will also add JTAG and program data load emulation if required.

The resulting netlist is merged with other designs, and implemented on one of our gate arrays. We fabricate wafers, assemble and test prototypes, and deliver them back to you for approval.

The only customer requirements are to provide the netlist, and to evaluate the prototypes. We take care of the rest.

EasyWire

The Tekmos EasyWire program supports FPGA conversions directly from the bitstream. This is necessary when the original design files have been lost or are no longer available.

Tekmos extracts your netlist directly from your binary bitstream. We then re-implement your design as a low cost, pin-compatible ASIC.

The Easywire program current supports both Xilinx 4000 and 3000 families. The datasheet is available here.

CPLD to ASIC Program (CAP)

The CAP program provides a very low cost path for the implementation of small designs into an ASIC. In the CAP program, Tekmos partitions a gate array into 10K gate sections. Each CAP design occupies one or more of these sections. The gate array also contains logic that will enable or disable a given design, depending on a chip select function which is controlled through a bond option.

The Designs

The CAP program will accept any design as long as it meets the overall requirements of

A design may also contain analog components, such as differential inputs, ECL outputs, oscillators, or voltage references. We will have to review such designs to insure that the analog components are compatible with our gate arrays.

It is not necessary for the existing design to be implemented in a CPLD. It could be a new design, or an existing ASIC, or an FPGA. If the design contains a RAM, it must still fit within the 10K gate limit. (1 RAM bit =~ 6 gates). Designs larger then 10K can still be supported through the use of adjacent sites. Large designs face a higher NRE charge, but receive the same manufacturing price.

Ideally, you will provide us with a test vector that will exercise the design. If not, then we will have to generate test vectors for you. Generating test vectors will increase the NRE.

Finally, you must provide us with a pinout for your device. The Tekmos gate arrays are quite flexible, and can adapt to any existing pinout.

The Flow

Every 4 to 8 weeks, Tekmos assembles a design consisting of a mixture of new prototypes and mature designs with production requirements. Photomasks are made, and we run a production lot of wafers. The wafers are assembled using a unique bond diagram for each design. The packaged parts are then tested, and delivered to our customers.

The Economics

The basic NRE is $10K per CAP slot, with a maximum of $40K. If we have to generate test vectors, there will be another $5K to $10K of engineering charges. There may be additional NRE charges if the design contains analog components. There are no charges for re-spins, no matter what the cause. It truly is a Non-Recurring Engineering charge.

Unit prices vary depending on the packaging and the order quantities. Our minimum order is 1,000 units. Larger orders may contain multiple line items, with each line item having a minimum of 1000 units. As an example, 5K units of a small design (<20K gates) in a 44 pin PLCC package would cost $5.54 each.

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