- Exact replacement of existing FPGAs, including Xilinx, Altera, Actel, Lattice and many others
- Identical package footprint means no board redesign
- Emulation of initialization sequence
- Emulation of JTAG circuit
- 0.35u Technology for older FPGAs
- 0.18u Technology for newer FPGAs
- Easy engineering interface. We work from your existing files
- Design recreation from programming files on some devices
- Flexible supply pin placement
- Automatic Test Program Generation (ATPG)
- Small or large production quantities supported
Major Customer Benefits
- Save 50% or more on cost of FPGAs / CPLDs
- Solve product obsolescence issues
- Guaranteed to work – no risk
- Fast turnaround on most FPGA replacements
FPGA conversions consist of reimplementing an FPGA design into an ASIC. There are a number of reasons to convert a design. An ASIC will have lower unit cost, lower power, higher performance, and more package flexibility. These benefits have to be weighed against the NRE charges, and the lack of reprogramability.
Tekmos provides customers with comprehensive engineering support. We accept designs on an "as is" basis, translate them into our internal cell libraries, and perform the engineering work necessary for a successful conversion.
FPGA Conversion Flow
Tekmos accepts designs in any format. Most designs arrive as FPGA netlists. We also convert ASIC netlists that have been implemented in another vendor’s library.
We request that the customer provide us with the original design files, along with any simulations that may exist. We can accept either pre-synthesis RTL level designs, or gate level designs.
In cases where the validity of the design files is in question, Tekmos can verify the design by comparing the simulated performance against actual results derived from the FPGA.
Simulations and Sign-Off
Original simulations (if they exist) will be enhanced with Tekmos generated simulations and used for production testing.
Replacing an FPGA or existing ASIC means that Tekmos is responsible for the post-route signoff. Customer participation, while optional, is encouraged.
The design will be fabricated, assembled, and tested. Prototypes are available in about 10 weeks after tape-out.
The data brief is available here: pdf FPGA Conversions (216 KB)