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The Tekmos Solution for Your System in a Package

The following post is of our recently revised Unify - Asics for Your System in a Package web page:

The Tekmos Solution for Your System in a Package

Tekmos provides a fast and low cost solution to integrate customer designs into a small form factor package using its unique low cost die stacking capabilities. There is significant time to market advantages merging various chips into a vertical stack to optimize integration and eliminate large NREs and high risk.  The Tekmos Unify solution includes a design and manufacturing service to handle all engineering from design through production shipment of final tested products.  This service is ideal for companies wishing to integrate their standard ICs to permit more room for other features or special batteries to expand features and extend the operating life of their products. 

Why Unify?

There are applications in which size is critical and non-negotiable.   This could be an ear-bud, a ring, or medical electronics that have to be swallowed.  WLCSP packages are small, but for more complex systems, they may not be small enough.  In these cases, the Tekmos Unify approach of a System in a Package can be the answer.

In the Unify approach, your system ICs are stacked on top of each other, producing a package that is only about 1 mm larger than the largest die, and is only 1 to 1.5 mm thick.

What types of Devices Can Be Included in Unify?

It the device is available in die form, it can be included in a Unify package.  We can also include resistors, capacitors, crystals, LEDs, accelerometers, and optical detectors.  There are limits that are mostly set by volume.  For example, a big capacitor is not going to fit in a small package.

What Does It Cost?

The base cost is your current bill of materials.  If you use a $4.00 microcontroller, it will still cost $4.00.  To this base cost, we have to add the packaging cost and the testing cost.  And that is going to vary depending both on the number of internal bond wires, and the time necessary to test the completed SiP.

There is usually an NRE charge for the substrate.  And this will vary depending on the number of layers necessary to interconnect your circuit.  There may need to be a package tooling charge if you require molded lenses, pressure holes, or other similar features.  Contact us for details.

Pinout Considerations

Most devices we stack have incompatible pinouts.  One chip may have a data bus that goes from D0 to D7, while another chip has a D7 to D0 order.  This can be resolved by having all chips connect to a common substrate.  This substrate can either be a BGA substrate or it can be a special ASIC.

Height Considerations

We prefer to stack the die in a pyramid configuration.  The height becomes an issue when the stack exceeds 4 die in height.  And sometimes, we may have two pyramids side by side.

Including an ASIC

Sometimes, it makes sense to consolidate some of the components into a mixed signal ASIC.  The ASIC also serves as a substrate, dealing with incompatible pinouts.  And it is a good way to add special interfaces and glue logic.  With over 800 successful ASICs, Tekmos has the experience necessary to support your design.

The ASIC can also contain JTAG circuitry which can assist in the testing of the completed SiP


Even though we start with Known Good Die (KGD), the completed system must be tested.  Assembly is not a perfect procedure.  Die can break, bond wires can short out, and so the completed SiP must be tested.  Knowing this, Tekmos designs our Unify parts to be tested.  This can be as simple as bringing out key nodes on unused pins, or developing a program for an internal micro that checks out functionality.  

Unify Your Design

Contact us today, and we can start shrinking your design.

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68HC705 Microcontrollers

Tekmos has a 68HC705 design that can be used to replace many variations of the 68HC05 and 68705 microcontrollers. Our first part is the TK68HC05B6 with 6K of ROM. Our second part is the user programmable TK68HC705C8A / TK68HC705C9A devices. These parts use flash memory as contrasted to the original part's One Time Programmable (OTP) EPROM. The 68HC705B16N and 68HC705B32 are available with a longer lead time.

The Tekmos 68HC05 has been carefully designed to duplicate the original 68HC05 on a clock for clock basis. This guarantees complete compatibility with existing code. Even timing loops will work perfectly.

Tekmos is currently seeking customers willing to evaluate our daughtercard-based breadboard in their system for the purposes of design verification.

Below is a list of 68HC705 microcontroller variants that are either available immediately or under development. If you need a version not listed here or have any questions please: Contact Us.

Part Number Description Datasheet
TK68HC05B6 TK68HC05B6 HC05 Microcontroller, 6K ROM pdf TK68HC05B6 (274 KB)
TK68HC05J1A TK68HC05J1A Microcontroller pdf TK68HC05J1A (1.14 MB)
TK68HC705B16 TK68HC705B16 Microcontroller pdf TK68HC705B (152 KB)  
TK68HC705B32 TK68HC705B32 Microcontroller pdf TK68HC705B (152 KB)  
TK68HC705C8A TK68HC705C8A Microcontroller  
TK68HC705C9A TK68HC705C9A HC05 Microcontroller, 16K Flash pdf TK68HC705C9A (125 KB)  
TK68HC805P18 TK68HC805P18 Microcontroller  
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The Design of a Masked ROM

This is the first in a series of articles covering the design of a masked ROM. It will cover the choices behind making a masked ROM, and the design of the ROM array.

The first question that should be asked is why would anyone ever design a masked ROM when you have flash? It is a good question, and we have two answers. The first is that this ROM is being designed for high temperature applications, and flash memories lose their data at high temperature. Flash memories use stored charge, which will leak away over time. The leakage rate is a function of temperature, and roughly doubles with every 10ºC rise in temperature. A 10-year life at 125ºC reduces to a matter of hours at 275ºC. And that is if the flash is built on a fully depleted SOI CMOS process, which most are not. This reduction in flash lifetime can be partially addressed by frequent refresh operations.

A second reason for considering a masked ROM is that many processes do not support the flash technology, whereas all processes can be used to make a masked ROM.

Once the decision has been made to make a masked ROM, the next choice is the architecture of the ROM array. There are two options: NAND and NOR. NAND has better density, but is slower, and uses more power. NOR has worst density, but is faster and uses less power. In the past, all our ROMs have used the NAND architecture. This time, we opted to use the NOR architecture. At high temperature, everything runs slower. In computer systems, the memory speed is usually the bottleneck, and so it makes sense to design the ROM for maximum speed. Our initial design goal is to have a sub 100 ns access time at 300ºC.

The design of the ROM array is about as simple as possible. Each ROM bit consists of a single N-channel transistor. The source is tied to ground, the gate is connected to the word line, and the drain is connected to the bit lines through the programmable contact. If there is a contact, the bit line goes to zero. If there is no contact, the bit line stays as a one.

The poly word line resembles a transmission line, and it can take the signal a long time to go from one end to the other. We are using a special high temperature process that does not support salicide. As a result, the poly is quite resistive. We address that by running a metal line over the poly, and connect it to the poly every 8 bits. This greatly improves the ROM speed for those bits located the furthest away from the word line drivers.

The next thing that we should worry about is the impedance of the ground lines. This is aggravated by the use of Tungsten as an interconnect metal. We have to use Tungsten because Aluminum has metal migration problems at elevated temperatures. In order to lower the ground impedance, we run perpendicular ground lines every 64 bit lines that convert the ground line from a single stripe into a grid. This allows every ground line in the array to help lower the impedance.

We do have to add additional bits. The initial ROM was an array of 512 rows by 512 columns, for a total of 256K bits. We will group every 8 bit lines together to produce a single output bit. This produces a 64 bit word. To improve reliability, we are adding ECC to the ROM, which will require 7 more output bits, or 56 more bit lines. And we need to add one additional bit line which is always programmed to provide a reference for the self-timing. This will be discussed later.

At this point, I have an array with 512 rows and 569 columns. I will discuss the word lines and their decodes in the next article.

Contact us today at This email address is being protected from spambots. You need JavaScript enabled to view it. for more information.

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Complying With New NIST Standards

The National Institute for Standards and Technology recently released a set of standards for cyber security. Defense contractors are required to implement these standards by the end of 2017, and that applies to Tekmos. We started off already being compliant with about half of the standards. Achieving compliance with the other half of the standards is more of a challenge.

One major area we are working on is formal documentation. The NIST standards require formal procedures for all aspects of cybersecurity. We already have informal procedures, but converting all of them to formal procedures is a major undertaking. The one advantage to creating all of this documentation is that it fits in with our AS9100 documentation we are creating for our certification audit later on this year.

The second area of work is the addition of card readers to each PC to only allow authorized users on each work station. At first, this seems straightforward, but becomes more complicated when our testers are taken into account. The testers are tightly coupled to engineering, and so are part of our network. But they also run independently, and we have one operator taking care of multiple tester / handler configurations. It is not clear how we will address this.

Another interesting area is the requirement of a whitelist for approved programs. Engineering will frequently try out new programs as part of their jobs. And so the procedures need to be written to allow this, while still providing security.

There is still a lot to do, but we are optimistic that we will be compliant by the deadline. And give the increased cyber threats these days, it is good to be improving our defenses.

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High Temperature Mixed Signals

High temperature electronics operate in one of the most demanding electronic environments. Junction leakage doubles with every 10ºC increase in temperature. For bulk silicon devices, the leakage becomes significant above 175ºC, and intolerable above 225ºC. And while digital logic can withstand some leakage, most analog circuits cannot.

Leakage is a problem that cannot be overcome with clever design tricks. It requires a different process. And that process is SOI (Silicon On Insulator).

In this process, oxygen is implanted beneath the devices. And the field oxide extends down to the implanted oxide layer, providing external isolation. Then, the diffusions are deep enough so that they too touch the buried oxide. This eliminates the bottom and sidewall junctions. And without a junction, there can be no junction leakage.

There is a small junction between the source / drain diffusions and the transistor channel. So while the junctions have not been totally eliminated, they have been reduced in area by a factor of 1,000. And that gives the SOI process an additional 100ºC of operation.

As with all engineering choices, there are tradeoffs. On the positive side, stray capacitance has been eliminated, along with the voltage dependency of diffused resistors. And with most wells tied to the transistor sources, the body effect has been eliminated.

On the negative side, layout density is decreased, and overall layout is more difficult. There are no vertical bipolar devices, just lateral ones. We do not have an EEPROM cell, so trimming becomes more complicated. And the 1u technology limits the circuit size.



To start with, anything that can be done in bulk silicon can also be done in the SOI process.

In the down-hole environment, there is demand for instrumentation amps, ADCs, DACs, and the occasional op-amp. All of these are easily made, and because of the lack of junctions, will have better performance than achieved with bulk devices.

Many down-hole measurements are made on low frequency signals, allowing Sigma-Delta ADCs to be used with up to 24-bit accuracy.

And since the SOI devices are totally isolated from the substrate, the analog supplies can be +/- 2.5v volts, and still work with a digital section operating from a 5 volt supply.

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