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Reprogrammable IP for High Temperature ASICs

Tekmos makes ASICs, which are definitely not programmable. But sometimes, customers need a little bit of programmability in an ASIC. Just look at the increase in FPGAs in modern SOC design. So, we decided to add reprogrammable IP to our high temperature ASIC product offering.

But what type of programmable IP? The high temperature process we use has limits, and one of the main limits is density. So, we decided to start with something small like a PAL. PALs (Programmable Array Logic) have been around for years. They were one of the first programmable devices, and lead the way into the development of FPGAs.

We have one other issue with our technology, and that is it does not support non-volatile memories. Stored charge memories leak away at high temperature. So, we decided to make a RAM based PAL. We chose to make a 22V10 equivalent PAL.

Starting with PALs has several advantages. First, the schematic is known, which simplifies the reverse engineering. Most of the work involves replacing the fuse array with a RAM. One interesting engineering point was the design of the wired-AND gate that the fuses are attached to. Most PALS used a pull-up resistor, and allowed the inputs to pull it low. This has the simplest layout, but continuously draws high current. And we were concerned that the increased leakages experienced at high temperature would cause this architecture to fail. So, we instead opted to build a discrete, 44-input AND gate. The layout is more complicated, but it has superior performance.

Another advantage of copying existing PALs is that the programming instructions are a JEDEC standard. If we maintain fuse compatibility, there are a number of existing software programs that can be used to develop circuits. And most of these programs are available at no cost. In some cases, the source code is also available.

Interfacing IP to the rest of the design is always an important issue. Our IP is designed to appear as a RAM to the rest of the ASIC. So, the interface becomes just a DMA into that RAM. We can set the data bus width to 8, 16, or 32 bits in size. Internally, the RAM is organized as 133 words of 44 bits.

Call us and find out how you can add reprogrammability to your next high temperature ASIC.

To learn more contact: This email address is being protected from spambots. You need JavaScript enabled to view it..

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Replacing Obsolete Flash Memories

Flash memories have been around long enough so that the original parts have gone obsolete. And while larger flashes could be used to replace older flashes, there are frequently differences in operating voltages, packaging, and programming algorithms which make this impractical.

Tekmos has gotten around these issues by designing an ASIC to serve as an interface between the outside system and the newer flash. Tekmos then combines the flash and our ASIC in a single package using stacked die assembly techniques. This produces as drop-in replacement for the original part that can be manufactured in any quantity.

Voltage Compatibility

Many older flash memories ran off of 5 volts. As the technology advanced, they switched to a 3 volt supply, but had 5 volt interfaces. Once the technology passed 130 nm, the parts became 3 volt only. To replace these parts, the Tekmos ASIC provides level translators and an internal voltage regulator.

The level translators provide the 5 volt to 3 volt translation on the address and control lines, and a bidirectional translation for the data bus. Level translators work well, but they require time to work. This time is on the order of 8 ns, and since we need to have translators on both the address and data lines, this will add about 16 ns to the Flash access time. And that sets a lower bound on how fast of a Flash we can replace. Using 55 ns flash, we produce a part that can be no faster than about 75 ns. This number will increase if we have to include additional circuitry to mimic other flash functions.

The ASIC also has to provide a 3.3 volt power supply for the flash. Flash memories have unusual power supply requirements. When they are being programmed, the supply current increases from idle to maximum in a few nanoseconds. This can be faster than a traditional voltage regulator can respond to. If that is the case, the power supply can droop, which could cause the flash to abort its write cycle, and then reduce the current draw. We address this by having a very high response speed voltage regulator which we designed. The price we pay for a quick response regulator is a limited input voltage range. Fortunately, most flash memories have a 10% tolerance on the input supply, which is well within the range of our regulator.

Programming Algorithm Compatibility

There are two main algorithms used to program Flash memories. These are the Intel / Micron algorithm and the Spansion / Fujitsu algorithm. In addition, really old Flash memories did not have an unlock algorithm. Instead, they used the presence of a programming voltage to initiate programming.

The best solution is to use a modern flash that has the same programming algorithm. We can tie off the upper address lines, and have a good match.

For the older chips, such as the 28F010, there are no existing Flash memories with the same programming algorithm. In those cases, we have to detect the programming cycle, and generate our own program sequence. The downside of this is that the additional circuitry in the address and data paths adds another 5 to 10 ns to the access time. Fortunately, many of the older Flash memories were slower, and so we have the margin. One possible problem with this approach is that if the programmer removes the voltage from our part at the end of the programming cycle, and our internal circuitry has not finished writing or erasing the past, then the write / erase operation can fail.

Sector Compatibility

It is desirable that the sector architecture of the new part match, or at least be compatible with the sectors used in the old part. We may be able to use address mapping to match the sector sizes. For example, a 64 KB sector could be used to replace a 32 KB sector. Typically, the newer Flash memories are larger, and that allows us flexibility in mapping the sectors. Note that the presence of sector mapping circuitry will add another 5 ns to the access time.

High Voltage Inputs

The really older flashes used the presence of a programming voltage (typically about 12 volts) to trigger a write / erase cycle. They also used this high voltage on pin A9 to read the manufacturer's ID. This high voltage poses a problem for our ASICs, which can be damaged by voltages in excess of 5.5 volts. Our solution is to use a series resistor to limit the voltage on the chip, and then use a lateral PNP transistor to detect the presence of the programming voltage.

Special Features

In some cases we must have our chip provide the original manufactures codes for part number and ID in order to maintain software compatibility. This can be done by intercepting the request, and taking over the data bus. Then we can provide whatever information is required.

Tekmos Flash Products

Tekmos makes 5 flash replacements. These are the TK17LV040 FPGA serial programming memory, and the TK28F256, TK28F512, TK28F010, and TK28F020 parallel flashes. We have other sizes under development.

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Word Line Drivers

In my last article, I discussed the design of the ROM bits. This article will cover the word line drivers.

Our ROM has 512 word lines. A brute force approach would use a 10-input AND gate to decode each word line, nine inputs for the address lines, and the tenth input to disable all word lines during precharge. But 10-input AND gates are both large and slow, so a better way must be used.

We use a 2-to-4 demuxer for eight of the address lines. The ninth address line is gated with the precharge. This allows a 5-input AND gate to be used instead of the 10-input gate. But this solution also has problems. In a NOR ROM, the word line drivers must be the same height as the ROM bit. And that is not enough room to put in a AND gate.

The next solution is to create a double height word driver that can decode both words. The schematic changes to a 4 input NOR gate that drives a pair of 2-input NAND gates, each driving a word line through inverters. This is a tight fit, but can be made to work by mirroring each dual word line driver so that they can share common supplies. Three of the four inputs of the NOR gate are common between the two mirrored drivers, and that saves more room.

The NOR and NAND gates are minimum sized devices, while the word line has 569 loads. In order to drive large loads, it is necessary to use a chain of inverters, each one being stronger than the preceding one. The optimum ratio between inverters is "e". But using "e" as the ratio results in a very large inverter driving the word line. And that means 512 large inverters for all the word lines.

We resolve this by letting the final ratio be a larger number. There is a tradeoff between reducing the inverter size, which increases the ROM access time, but reduces the area and reduces the peak current draws. After multiple spice runs, we set the output inverter ratio to be about 95:1. This also allows the inverter chain to be three inverters long. One thing that worked in our favor is that the bit cells start to conduct as soon as the word lines exceed the N-channel threshold, which is close to the starting voltage.

The address lines A6:A14 control the word decode. We have the option of latching them during the ROM read cycle, or not. If we choose to latch them, then we can either include the latches in the ROM core, or latch them externally. It is not required to latch the addresses, but it is safer to do so. Our final decision will be determined by the physical layout. If there is room for the latches, then we will add them. If not, we will leave that as an option for the chip level designer that uses this ROM core.

In the next column, I will cover the bit line muxes, the sense amps, and the ECC logic.

Contact us today at This email address is being protected from spambots. You need JavaScript enabled to view it. for more information.

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The Tekmos Solution for Your System in a Package

The following post is of our recently revised Unify - Asics for Your System in a Package web page:

The Tekmos Solution for Your System in a Package

Tekmos provides a fast and low cost solution to integrate customer designs into a small form factor package using its unique low cost die stacking capabilities. There is significant time to market advantages merging various chips into a vertical stack to optimize integration and eliminate large NREs and high risk.  The Tekmos Unify solution includes a design and manufacturing service to handle all engineering from design through production shipment of final tested products.  This service is ideal for companies wishing to integrate their standard ICs to permit more room for other features or special batteries to expand features and extend the operating life of their products. 

Why Unify?

There are applications in which size is critical and non-negotiable.   This could be an ear-bud, a ring, or medical electronics that have to be swallowed.  WLCSP packages are small, but for more complex systems, they may not be small enough.  In these cases, the Tekmos Unify approach of a System in a Package can be the answer.

In the Unify approach, your system ICs are stacked on top of each other, producing a package that is only about 1 mm larger than the largest die, and is only 1 to 1.5 mm thick.

What types of Devices Can Be Included in Unify?

It the device is available in die form, it can be included in a Unify package.  We can also include resistors, capacitors, crystals, LEDs, accelerometers, and optical detectors.  There are limits that are mostly set by volume.  For example, a big capacitor is not going to fit in a small package.

What Does It Cost?

The base cost is your current bill of materials.  If you use a $4.00 microcontroller, it will still cost $4.00.  To this base cost, we have to add the packaging cost and the testing cost.  And that is going to vary depending both on the number of internal bond wires, and the time necessary to test the completed SiP.

There is usually an NRE charge for the substrate.  And this will vary depending on the number of layers necessary to interconnect your circuit.  There may need to be a package tooling charge if you require molded lenses, pressure holes, or other similar features.  Contact us for details.

Pinout Considerations

Most devices we stack have incompatible pinouts.  One chip may have a data bus that goes from D0 to D7, while another chip has a D7 to D0 order.  This can be resolved by having all chips connect to a common substrate.  This substrate can either be a BGA substrate or it can be a special ASIC.

Height Considerations

We prefer to stack the die in a pyramid configuration.  The height becomes an issue when the stack exceeds 4 die in height.  And sometimes, we may have two pyramids side by side.

Including an ASIC

Sometimes, it makes sense to consolidate some of the components into a mixed signal ASIC.  The ASIC also serves as a substrate, dealing with incompatible pinouts.  And it is a good way to add special interfaces and glue logic.  With over 800 successful ASICs, Tekmos has the experience necessary to support your design.

The ASIC can also contain JTAG circuitry which can assist in the testing of the completed SiP


Even though we start with Known Good Die (KGD), the completed system must be tested.  Assembly is not a perfect procedure.  Die can break, bond wires can short out, and so the completed SiP must be tested.  Knowing this, Tekmos designs our Unify parts to be tested.  This can be as simple as bringing out key nodes on unused pins, or developing a program for an internal micro that checks out functionality.  

Unify Your Design

Contact us today, and we can start shrinking your design.

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68HC705 Microcontrollers

Tekmos has a 68HC705 design that can be used to replace many variations of the 68HC05 and 68705 microcontrollers. Our first part is the TK68HC05B6 with 6K of ROM. Our second part is the user programmable TK68HC705C8A / TK68HC705C9A devices. These parts use flash memory as contrasted to the original part's One Time Programmable (OTP) EPROM. The 68HC705B16N and 68HC705B32 are available with a longer lead time.

The Tekmos 68HC05 has been carefully designed to duplicate the original 68HC05 on a clock for clock basis. This guarantees complete compatibility with existing code. Even timing loops will work perfectly.

Tekmos is currently seeking customers willing to evaluate our daughtercard-based breadboard in their system for the purposes of design verification.

Below is a list of 68HC705 microcontroller variants that are either available immediately or under development. If you need a version not listed here or have any questions please: Contact Us.

Part Number Description Datasheet
TK68HC05B6 TK68HC05B6 HC05 Microcontroller, 6K ROM pdf TK68HC05B6 (274 KB)
TK68HC05J1A TK68HC05J1A Microcontroller pdf TK68HC05J1A (1.14 MB)
TK68HC705B16 TK68HC705B16 Microcontroller pdf TK68HC705B (152 KB)  
TK68HC705B32 TK68HC705B32 Microcontroller pdf TK68HC705B (152 KB)  
TK68HC705C8A TK68HC705C8A Microcontroller  
TK68HC705C9A TK68HC705C9A HC05 Microcontroller, 16K Flash pdf TK68HC705C9A (125 KB)  
TK68HC805P18 TK68HC805P18 Microcontroller  
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