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High Temperature Mixed Signals

High temperature electronics operate in one of the most demanding electronic environments. Junction leakage doubles with every 10ºC increase in temperature. For bulk silicon devices, the leakage becomes significant above 175ºC, and intolerable above 225ºC. And while digital logic can withstand some leakage, most analog circuits cannot.

Leakage is a problem that cannot be overcome with clever design tricks. It requires a different process. And that process is SOI (Silicon On Insulator).

In this process, oxygen is implanted beneath the devices. And the field oxide extends down to the implanted oxide layer, providing external isolation. Then, the diffusions are deep enough so that they too touch the buried oxide. This eliminates the bottom and sidewall junctions. And without a junction, there can be no junction leakage.

There is a small junction between the source / drain diffusions and the transistor channel. So while the junctions have not been totally eliminated, they have been reduced in area by a factor of 1,000. And that gives the SOI process an additional 100ºC of operation.

As with all engineering choices, there are tradeoffs. On the positive side, stray capacitance has been eliminated, along with the voltage dependency of diffused resistors. And with most wells tied to the transistor sources, the body effect has been eliminated.

On the negative side, layout density is decreased, and overall layout is more difficult. There are no vertical bipolar devices, just lateral ones. We do not have an EEPROM cell, so trimming becomes more complicated. And the 1u technology limits the circuit size.



To start with, anything that can be done in bulk silicon can also be done in the SOI process.

In the down-hole environment, there is demand for instrumentation amps, ADCs, DACs, and the occasional op-amp. All of these are easily made, and because of the lack of junctions, will have better performance than achieved with bulk devices.

Many down-hole measurements are made on low frequency signals, allowing Sigma-Delta ADCs to be used with up to 24-bit accuracy.

And since the SOI devices are totally isolated from the substrate, the analog supplies can be +/- 2.5v volts, and still work with a digital section operating from a 5 volt supply.

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Complying With New NIST Standards

The National Institute for Standards and Technology recently released a set of standards for cyber security. Defense contractors are required to implement these standards by the end of 2017, and that applies to Tekmos. We started off already being compliant with about half of the standards. Achieving compliance with the other half of the standards is more of a challenge.

One major area we are working on is formal documentation. The NIST standards require formal procedures for all aspects of cybersecurity. We already have informal procedures, but converting all of them to formal procedures is a major undertaking. The one advantage to creating all of this documentation is that it fits in with our AS9100 documentation we are creating for our certification audit later on this year.

The second area of work is the addition of card readers to each PC to only allow authorized users on each work station. At first, this seems straightforward, but becomes more complicated when our testers are taken into account. The testers are tightly coupled to engineering, and so are part of our network. But they also run independently, and we have one operator taking care of multiple tester / handler configurations. It is not clear how we will address this.

Another interesting area is the requirement of a whitelist for approved programs. Engineering will frequently try out new programs as part of their jobs. And so the procedures need to be written to allow this, while still providing security.

There is still a lot to do, but we are optimistic that we will be compliant by the deadline. And give the increased cyber threats these days, it is good to be improving our defenses.

Contact us today at This email address is being protected from spambots. You need JavaScript enabled to view it. for more information.

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The TK89H51B family is based on the 8051 architecture, is designed to work in high temperature environments up to 210ºC. There are three versions, defined by package size. The "A" version has full functionality while the lower pin count "B" and "C" versions containing a subset of the functions.

The "A" version of the TK89H51B provides a non-multiplexed address and data bus, the 8-bit ADC, three additional parallel ports, and the SPI port. The "A" version also supports ISP, allowing for the downloading of programs into an existing system using HEX records. After the user program has been received, the processor jumps to location 0000 for further operation.

The TK89H51B family is made on a 0.6u bulk silicon technology process which has a long and successful history.

The TK80H51B family contains seven 8-bit bidirectional parallel ports, two external interrupt sources, three timer/counters, a serial port with a hardware interrupt capability and a frame error detect flag, power management, a programmable counter array (PCA), an 8-bit, 8-channel ADC, and a SPI port. These peripherals are supported by a multiple source, four level interrupt capability. The core processor contains 256 bytes of scratchpad RAM and another 256 bits of XRAM that can be used as program storage.

We have been using a "H" designator for the 8051 series to indicate high temperature. But now that we have both bulk and SOI parts underway, we find it necessary to create new part numbers. In the past, other 8051 vendors have differentiated their parts with a suffix, and so we followed that procedure. Here is our numbering system for the 0.6u, high temperature 8051s:

Device Package Description
TK89H51BA 68 Pin PGA With additional ports and ADC
TK89H51BB 48 Pin DIP With ADC
TK89H51BC 40 Pin DIP Original 8051 footprint


Request for Product Information

To request information click here TK89H51B

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Tekmos serves several high reliability markets, such as aerospace, military, and oil. It is therefore only natural that much of our internal R&D efforts are directed toward increasing the reliability of our products. One of these efforts is aimed at improving the reliability of processors. One way to do so is using a triple redundancy for all flops in the processor, a technique called RHBD (Rad-Hard By Design). This works, but is a brute force approach that at a minimum, triples the circuit size. We have another approach that may only add a 30% overhead.

To verify this approach, we need a processor to try it out on. There are many processors out in the market, but they come with licensing fees and restrictions on changes to the internal architecture. And we need to modify the internal architectures.

So, we chose the RISC V processor, which is an open source processor from Berkley. An interesting aspect of this processor is that it is defined by the instruction set, rather than the hardware. The RISC V processor is finding increasing acceptance, and is supported by several development tools.

Our first step was to get the basic design up and running in our simulator. Then came the more difficult task to fully understand the design. This is where we are now. Next, we use the RISC V as a test bed to prove out our reliability concepts. What is next beyond that is a little uncertain, and is more of a marketing decision. Check back with us in a year and see how it turns out.

Contact us today at This email address is being protected from spambots. You need JavaScript enabled to view it. for more information.

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Burn-In and Reliability Testing

Tekmos offers Burn-In and Reliability Testing services.  The requirements can vary from part to part, and Tekmos can customize these services to meet your exact needs.


The failure rate of integrated circuits over time follows what is called the "bathtub" curve.  There is a high rate of infant mortality initial failures.  Then the failure rate drops, only to increase at the end of life due to wear out failures.  The reliability of a part can be enhanced by providing a burn-in at elevated temperatures prior to usage.  This burn-in is typically somewhere from 40 to 160 hours in length, and is done at a temperature of between 70ºC and 125ºC.  It is important that the parts be exercised during this burn-in.  It is also good to monitor the part performance during burning, so that the time point of failures can be detected.  That data can be used to set the optimum burn-in length.

One of the major costs of a burn-in is the boards used for the burn-in.  This is a tradeoff between the cost of the sockets on the boards, the number of boards needed, and the total number of parts to be burned in.  Major manufacturers with very high volumes will invest in high quality sockets that will cost from $50 to $100 per chip.  This socket cost adds up quickly.

In addition to the oven capacity, Tekmos also has in-house design and layout capability for both the burn-in boards and driver boards (if needed).

Reliability Testing 

There are several over-lapping reliability testing specifications.  Specifically, these are the JESD47I, the AEC-Q100, and the military Mil Spec 883.  These require subjecting several lots to stresses, and then looking for failures.  Some tests are for the die, and other tests check the packages.  Because of the standardization of the packages, the die tests are the most important.  And the main die test is the HTOL, or High Temperature Operating Life.  In this test, the parts are typically operated at 125ºC for 1000 hours.  If the parts cannot be tested in the oven, the parts will be periodically pulled from the oven, tested, and re-inserted back into the oven.  Common read points are at 48, 96, 168, 250, 500, and 1000 hours. 

Parts that fail are subjected to a failure analysis.  The type of failure analysis depends on the nature of the failure.  Some failures are obvious, such as a pin breaking off.  Other failures may need to be decapsulated, and analyzed optically.  Failure analysis is engineering intensive, and Tekmos can provide that support.

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