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TK68020 Microprocessor

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Features

  • Addressing Mode Extensions for Enhanced Support High-Level Languages
  • Object-Code Compatible with Earlier M68000 Microprocessors
  • New Bit Field Data Type Accelerates Bit-Oriented Applications e.g., Video Graphics
  • An On-Chip Instruction Cache for Faster Instruction Execution
  • Coprocessor Interface to Companion 32-Bit Peripherals-the MC68881 and MC68882 Floating-Point Coprocessors and the MC68851 Paged Memory Management Unit
  • Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple
  • Instructions To Be Executed Concurrently
  • High-Perfrmance Asynchronous Bus Is Non-multiplexed and Full 32Bits
  • Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peripherals
  • Full Support of Virtual Memory and Virtual Machine
  • Sixteen 32-Bit General-Purpose Data and Address Registers
  • Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers
  • Eighteen Addressing Modes and Seven Data Types
  • 4-Gbyte Direct Addressing Range
  • 16-Mbyte Direct Addressing Range
  • Selection of Processor Speeds 16.67.20, 25, and 33.33 MHz
  • Available in modified 132 pin BQFP (Using adaptor)- see mechanical data section.

 

 

General Description

The TK68020 is a functional equivalent of the Motorola M68020 and they are pin-for-pin compatible. It is a full 32-bit implementation of the M68000 family of microprocessors from Motorola.

The TK68020 is a full 32-bit implementation of the 68000 family of microprocessors from Motorola. The TK68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.

The TK68020 is object-code compatible with earlier members of the 68000 family and has the added features of new addressing modes in support of high-level languages, an on-chip instruction cache, and a flexible coprocessor interface with full IEEE floating-point support available. The internal operations of this microprocessor operate in parallel, allowing multiple instructions to be executed concurrently.

The asynchronous bus structure of the TK68020 uses a non-multiplexed bus with 32 bits of address and 32 bits of data. The processor supports a dynamic bus sizing mechanism that allows the processor to transfer operands to or from external devices while automatically determining device port size on a cycle-by-cycle basis. The dynamic bus interface allows access to devices of differing data bus widths, in addition to eliminating all data alignment restrictions.

Documentation

The data sheet is available here: pdf TK68020 (1.11 MB)

 

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