Tekmos Talks

 
A Newsletter for the Semiconductor Industry
December 2017 
Reprogrammable IP for High Temperature ASICs

Tekmos makes ASICs, which are definitely not programmable. But sometimes, customers need a little bit of programmability in an ASIC. Just look at the increase in FPGAs in modern SOC design. So, we decided to add reprogrammable IP to our high temperature ASIC product offering.

But what type of programmable IP? The high temperature process we use has limits, and one of the main limits is density. So, we decided to start with something small like a PAL. PALs (Programmable Array Logic) have been around for years. They were one of the first programmable devices, and lead the way into the development of FPGAs.

We have one other issue with our technology, and that is it does not support non-volatile memories. Stored charge memories leak away at high temperature. So, we decided to make a RAM based PAL. We chose to make a 22V10 equivalent PAL.

Starting with PALs has several advantages. First, the schematic is known, which simplifies the reverse engineering. Most of the work involves replacing the fuse array with a RAM. One interesting engineering point was the design of the wired-AND gate that the fuses are attached to. Most PALS used a pull-up resistor, and allowed the inputs to pull it low. This has the simplest layout, but continuously draws high current. And we were concerned that the increased leakages experienced at high temperature would cause this architecture to fail. So, we instead opted to build a discrete, 44-input AND gate. The layout is more complicated, but it has superior performance.

Another advantage of copying existing PALs is that the programming instructions are a JEDEC standard. If we maintain fuse compatibility, there are a number of existing software programs that can be used to develop circuits. And most of these programs are available at no cost. In some cases, the source code is also available.

Interfacing IP to the rest of the design is always an important issue. Our IP is designed to appear as a RAM to the rest of the ASIC. So, the interface becomes just a DMA into that RAM. We can set the data bus width to 8, 16, or 32 bits in size. Internally, the RAM is organized as 133 words of 44 bits.

Call us and find out how you can add reprogrammability to your next high temperature ASIC.

To learn more contact: This email address is being protected from spambots. You need JavaScript enabled to view it..

From the Desk of the President, Lynn Reed
20141210 Lynn 111 
        Lynn Reed, President

High Temperature ROM Design-Sense Amps

In the previous two articles, we discussed ROM bits and word drivers. In this article, we will discuss the sense amps. Or more accurately, we will discuss the bit line precharge, the multiplexor, the sense amps, and the output latch.

In the ROM, the bits can only pull to zero. To ever get to a logic one, we use a precharge circuit. That is a fancy name for a P-channel transistor. In between read cycles, the bit lines are kept precharged. When a read occurs, the precharge lines are turned off, and then a single word line is turned on. Depending on whether that bit has been programmed, the bit line will either remain at a one, or be pulled down to a zero. After the end of the cycle, the bit lines are precharged back to the one level. The size of the precharge transistor is not that critical. It must be large enough to precharge the bit line before the next cycle occurs. Generally, this can be accomplished in 3 or 4 nanoseconds.

The most difficult thing about the precharge is the layout. Since there is one for every bit line it must fit within the width of a bit. In our case, the bit was so narrow that we could not make the precharge fit. As a result, we staggered the precharge transistors, taking up twice the height so that we could maintain the required width.

After the precharge is an 8:1 mux. This consolidates 8 bit lines down to a single signal that will feed the sense amp. The mux is built out of N-channel transistors. They are arranged as 2:1 muxes in 3 stages, going from 8 to 4 to 2 to 1 signal. There is a slight complication in that each individual mux stage also requires a precharge. So, in addition to the 8-bit line precharges, we have to add 7 mux precharges. The mux is controlled by address lines A3, A4, and A5.

The sense amp is quite different in a ROM than in a RAM. In a RAM, there are complimentary bit lines available, and the sense amp makes a differential measurement. Differential measurements are quite easy to make in MOS technologies. However, in the ROM, there is only a single bit line available. One might create a voltage reference, but there are difficulties in making a valid reference, and the margin available is only half that of a true differential signal. Instead of a voltage reference, we use time as a reference. We add one additional bit line to the ROM that is always programmed as a zero. This extra bit line closely tracks the performance of the rest of the ROM. So, when it reaches a zero level, we know that sufficient time has passed for any other bit line that is switching to a zero to reach a zero level. This turns the sense amp into a simple inverter. This inverter then feeds a latch. We make the latch transparent at the beginning of the cycle, and close it when the reference bit line reaches a zero.

Starting from 568 bit lines, the muxes narrow it down to 71 bits, and those are stored in latches. The number 71 comes from 64 data bits and 7 error correcting bits. In our next article, we will cover how the ECC circuitry works, and how we wind up with a final data bus of 8, 16, or 32 bits in size.

Read more of Lynn's blog...

Contact us today at This email address is being protected from spambots. You need JavaScript enabled to view it. for more information.

Inside Tekmos
turkeyday

Tekmos Thanksgiving Celebration

Every year, on the Friday before Thanksgiving, we have a company spread. The company covers the Turkey, and everyone else brings something.

Since everyone makes their best dish, we have a very good meal. Jon Gehm experimented with a cherry pie, covered with whipped cream containing Madagascar vanilla. He was disappointed with the results, but no one else was, and there was none left over. Rick Holman had some excellent creamed corn with real cream. And of course, there was a lot of turkey, dressing, and gravy.

There were some leftovers, but those were taken home by our younger employees, who are still hungry from their college days.

Technology Innovation

Tekmos Product Technical Notes

puzzle

November was a busy month for us. We received first silicon of a revision to our TK89C668 microcontroller. This was an analog adjustment to a pull-up current that was not centered on specification. We characterized the part, and found the adjusted current was an exact match to the design goals. This is proof that Spice simulations work.

A few months ago, we invested in a probe test for our highest volume part. The first production material that we probed arrived at final test this month. This allows us to separate the fabrication yield from the assembly yield. We were surprised by how good a job our assembler is doing, as we now have almost no failures at final test.

We also taped out on our new replacement for the 80C51RA2, 87C51RA2, 87C51RB2, 87C51RC2 and 87CRD2 microcontrollers. With 3 different package styles, that will provide us with 15 prototype lots to evaluate. It now looks like they will arrive back at Tekmos a few days before Christmas. We will have something to do should we tire of opening presents.

Thank You for Reading Tekmos Talks

xmas

Thank you for reading Tekmos Talks and helping us celebrate 20 years. Call (512) 342-9871 or email Sales for more information.

Tekmos, 20 years of solutions.

Sincerely,

Lynn Reed, President

Logo new 3

7901 E. Riverside Dr. Building 2, Suite 150
Austin, TX 78744
Phone: (512) 342-9871
Fax: (512) 342-9873
Email: This email address is being protected from spambots. You need JavaScript enabled to view it.
Source: Tekmos, Inc.

 
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