Tekmos Talks

 
A Newsletter for the Semiconductor Industry
January 2017 
 

 2017

Welcome to Tekmos Talks 1st Edition for 2017. This month we will share Tekmos New Year Resolutions, Part III on Block Ram, talk about the Break Even Point for FPGA Conversions, and share Inside Tekmos Grad celebrations.

From the Desk of the President, Lynn Reed
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        Lynn Reed, President

2017 New Year's Resolutions

It is time for the 2017 New Year Resolutions. 2016 was a year of change for Tekmos, and so some of these resolutions may seem familiar.

Engineering

1. Start work on a 32-bit RISC processor.

Tekmos has a lot of 8 and 16-bit microcontrollers, but none in the 32 bit market.

2. Release a high temperature 8051 processor.

This part has been in development for a while, but was placed on hold with the decline in the oil market. We see that market recovering in 2017.

3. Improve engineering design documentation and review procedures.

Tekmos needs to improve the design documentation and review procedures, in anticipation of achieving AS9100 certification. These are going to be based on the DO-254 specification.

4. Improve our test documentation and release standards.

We will formalize our test release procedures, including documentation.

Manufacturing

5. Redo our manufacturer traveler system to better incorporate different test flows.

Our manufacturing flow has developed many more options, and we need to revise our travelers accordingly.

6. Develop maintenance tools for our testers.

We doubled the number of testers we owned last year, and we need to continue to develop maintenance tools (actually specialized load boards) that will help us insure that our testers are working properly for production test.

Quality and Administration

7. Continue work on our AS9100 certification.

Our goal is to make substantial progress towards achieving our AS9100 certification.

8. Create data bases for customers and contacts.

Create another database for customer inquiries, and integrate it into a BPM flow.

Sales and Marketing

9. Develop a searchable customer mail database.

This is an IT project that we have been working on. The goal is to create a searchable database of all mail sent to or received from our customers and vendors.

10. Develop an ultra-high reliability strategy for the marketing of certain Tekmos microcontrollers.

Check back in December and see how well we did with our resolutions.

Part III Design of Dual Port RAM

Word Line Drivers

This is the third in a series of articles on the design of a dual port RAM.

A word driver decodes a specific address, and then drives the word line. In a dual port memory, there are two sets of word drivers, one for each port. The internal memory is organized in a 256 x 72 array, so there will be 256 word drivers.

At first glance, it would appear all that is needed for a word driver is an 8-input AND gate, followed by a buffer. But first glances are frequently wrong. There are actually 256 + 1 decodes, with the last decode being no decode at all. The bit lines are precharged before a read, and during that time, all of the bits must be deselected.

One could design a 9-input AND gate for the word line function, but that takes up too much room. A 9-input AND gate would take the form of three 3-input NAND gates, followed by a 3-input NOR gate. A better approach is to create a pre-decode, in which each group of two address lines is converted into a de-mixed 1 of 4 group. The word line driver then becomes a single 4-input NAND gate, with each input taking one of the group of 4 for each address line. Generating the no-decode state can be accomplished by forcing one of the address groups to an all-zero state.

There are different delays associated with each input of a logic gate. So, the address decode that can be forced to zero is connected to the fastest input.

It is necessary for the layout of the word line driver to be no more than one bit cell in height. This forces the cell to be wide, providing ample room for the address decodes to be routed.

Once the word signal has been decoded, it has to drive two transistors in each of the 72 bit cells. This is a large load, and the output should be buffered. More specifically, the output has to be buffered, buffered, and buffered again. The word line drivers must be optimized because the delay directly contributes to the read access time.

Our word line is made out of metal. Metal has a low resistance, so there is minimal RC delay along the word line. That was not always the case. In older technologies, the word line was frequently poly. Poly is much more resistive than metal, and so there was a significant RC delay along the word line. To minimize this, the address decode was placed in the middle of the RAM. This cut the RC delay in half.  Since we have metal word lines, we have more flexibility in where we place the decodes. For us, it makes more sense to put one word decode on one edge of the memory array, and put the other port's decode on the other side of the memory.

Our next article will cover the memory sense amps.

The Break Even Point

 Tekmos FPGA Header 675x250

The Breakeven Point on FPGA Conversions

An FPGA conversion consists of implementing an FPGA based design in an ASIC. There can be multiple reasons for doing this, such as reliability, power dissipation, or obsolescence. But the main reason is cost. ASICs will typically cost much less than an FPGA.

ASICs also have a NRE associated with them. So to realize any cost savings, the ASIC volume must be high enough so that the cumulative unit cost savings exceeds the NRE charges.

There is a time value of money. In order to justify an FPGA conversion, the volume should be high enough so that the breakeven point occurs within 6 to 9 months. Here is an example. Assume that the FPGA costs $40 each, and the ASIC costs $5 each. That is a savings of $35 per part. A typical FPGA to ASIC NRE will be on the order of $49,000. That puts the breakeven point at 1400 units. The conversion is economically justified with a 2,000 unit annual volume. The breakeven volume changes with the technology used in the ASIC, the cost of the FPGA, and the package type.

The breakeven point has also changed with time. Back in the mid-90s, the breakeven point was frequently below 1000 units. At the time, there were a number of companies providing FPGA conversion services. Companies such as AMIS, Chip Express, and Orbit Semiconductor. Many of the Japanese companies also offered the service, including NEC, Toshiba, KLSI, and Fujitsu. The FPGA companies successfully fought back by a combination of using more advanced technology nodes, and including large amounts of RAM. The presence of the RAM prevented the ASIC companies from offering the same circuit while using an older technology. The increased use of lower supply voltages also worked against the ASIC companies, since their older technologies did not operate as well when using reduced supplies. By 2005, the FPGA conversion business was gone, along with most of the ASIC suppliers.

Semiconductors are a highly dynamic business, and by 2012, the economics of FPGA conversion had changed again. The mask costs have dropped, and those fabs that allow Multi-Level Masks (MLMs) have seen the mask cost drop by another 75%. The power supplies have stabilized between 1 and 1.2 volts. And while the FPGA technologies can provide more RAM, many applications do not need the extra RAM. As a result, FPGA conversion breakeven points have dropped to the point where conversions are again economical at the 1000 to 2000 unit range.

Contact us to see if a FPGA conversion makes sense in your application.

Inside Tekmos

Tekmos Team Members Celebrate

kelseyTekmos Team Members Kelsey Mehlhorn, engineer and intern, Jaime Perez, celebrated December 2016 by graduating from Texas State University Ingram School of Engineering with their Bachelor of Science degrees in Manufacturing Engineering and Electrical Engineering respectively. Tekmos executives and staff were on hand to watch the two graduates walk to receive their diplomas. John Gehm, Kelsey's supervisor is photographed here. Later friends and family watched Kelsey take a plunge into the San Marcos River, a school tradition.

jaimeKelsey and Jaime celebrated additional kudos by winning awards for their Senior Capstone projects. Kelsey's team won 1st place in Manufacturing Engineering for their Olfactory Delivery System for NASA. Jaime's team won 3rd place in Electrical Engineering for their project on Keyway Detection. Tekmos heartily congratulates Kelsey and Jaime!

Thank You for Reading Tekmos Talks

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Thank you for reading Tekmos Talks. Call (512) 342-9871 or email Sales for more information.

Tekmos' Unify for your SiP , with continued innovation.

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Source: Tekmos, Inc.

 
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