|A Newsletter for the Semiconductor Industry|
Welcome to Tekmos Talks March 2017. This month we will discuss Altera FPGA conversions, Part V of Dual Port Ram-Memory, launch a new product, and share Inside Tekmos' Cookout.
|From the Desk of the President, Lynn Reed|
Altera FPGA Conversions
Altera announced the discontinuation of many of their FPGA lines last December. This includes the MAX, Flex, and early Acex and Apex families. Customers are given the opportunity to make a last time buy of these products. And for many customers, this is the best choice.
But for some customers, it is not the best choice. Making a last time buy means that you have a reasonable understanding of your future requirements, and you are willing to tie up capital to buy a multi-year supply of these products. If your products are continuing to do well, or even growing in volume, then it is both difficult and risky to forecast the entire future demand, and an FPGA conversion should be considered.
The FPGA conversion will generally cost a lot less than the original FPGAs. But conversions also have an associated NRE. This produces a breakeven volume point where the unit savings equal the NRE charges. If this point is reached in 6 to 9 months, a conversion is economical. If it takes longer, then the conversion must be justified by other means, such as strategic availability.
Tekmos has developed several methods of reducing the NREs, making it possible to lower the breakeven point. The first is what we call a merge. In a merge, we combine multiple designs on a single piece of silicon. Each individual design is activated through a bond option during assembly. This allows all the designs to share the costs of a mask set and a wafer run, which are the main components to a NRE charge. Of course, each design must be individually converted, assembled, and tested. Still, the NRE charge per part is much less than the charges if each part was individually converted.
Merges have another advantage. By combining multiple designs on a single die, the volume for that die is the combined total for all the devices in the merge. Wafer fabs will make quarter half lots, but there is a financial penalty in doing so. A merge may allow a single order for multiple parts to obtain better wafer pricing.
Another way to reduce costs is to use a more advanced technology for the FPGA conversion. For 180nm and up, all the NRE charges are equivalent. In many cases, the operating voltage will determine the technology. As a very rough rule of thumb, the technology * 10 is equal to the maximum operating voltage. This sets the minimum die size, and that sets the manufacturing costs.
Tekmos can get around this limitation by using an on-chip voltage regulator to produce the lower core voltages while allowing the I/O voltages to be the same as the original FPGA. Since the newer technologies have significant density advantages, this can result in a smaller die size, and thus a lower cost.
Or fill out the FPGA questionnaire form here.
Or to Request a Quote.
|Part V Design of Dual Port RAM, by Lynn Reed|
In this final article about RAM design, I am going to discuss the timing necessary to make the RAM work.
Between memory cycles, the RAM is in a precharge mode. All bit lines are being held at Vdd. All word lines are off. And the data latches are holding the last value that was read or written.
The cycle begins when a chip enable signal is clocked into a flop. In a synchronous RAM, the clock is the RAM clock. In an asynchronous RAM, the clock is derived from a change in address lines. The rest of the RAM timing is asynchronously derived from the output of this flop. This means that the end of one step triggers the next step. Here is the sequence of RAM timing:
Item 3, the read delay, is the difficult step. The time necessary for the bit cells to charge the bit lines is the major component of the memory access time. It needs to be just long enough for the bit lines to have enough differential voltage so that it can be detected by the sense amps. If it is too long, then the memory access time has been unnecessarily increased. But if it is too short, then the data cannot be reliably read, and the memory will fail. The trick is to create a delay of just the right length, plus a small bit of margin.
One way to do this is to add one additional bit line to the array, with the data in the bit cells connected to this line hard wired to zero. Since the extra bit line is part of the array, its timing will exactly duplicate the timing of the other bit lines. This bit line is fed into a ratioed inverter whose threshold is set just beyond the sensitivity of the sense amp. The buffers on the output of the inverter provide additional margin.
Setting the inverter threshold is a classic engineering tradeoff between speed and margin. While pure RAM designers go for speed, there are other considerations for ASIC RAM designers. This RAM is going in an embedded array that will be re-used in different applications. As a result, I must assume a wider temperature range. Instead of the commercial -40C to +85C, or the military -55C to +125C, I need to have it work -65C to +150C. Analog is always the weak link in a design, and I can't have the RAM be the first thing to fail. The design must also work over a wider supply range. The ASIC may be powered off a battery, which can require the minimum voltage to be on the order of a volt. And the easiest way to achieve these goals is to adjust the inverter threshold to give more margin at the expense of speed.
I can also build multiple inverters, and allow the metal programing options to select the inverter ratio. This lets me vary the speed versus margin on a customer by customer basis.
And that is how you build a dual-port block RAM.
|New Product Announcement|
A New Revision to the TK89C668
Tekmos is pleased to announce a revision to the popular TK89C668 microcontroller. Based on the 8051 architecture, this 5-volt microcontroller offers 64K of program storage, an I2C controller, and 8K of XRAM.
The TK89C668 was originally made at Plessey Semiconductor. Plessey made the decision to discontinue foundry services, and so the part was switched to the 0.35u fabrication line at the X-Fab Dresden facility. Plessey had been using a similar X-Fab process in their factory, resulting in minimal process differences between the two foundries.
Since we were forced to retool at X-Fab, we took advantage of the situation, and corrected all known errata on the part. We also improved the RAM design by replacing a traditional RAM with one made out of latches that has a superior voltage and temperature operating ranges.
The TK89C668 joins our TK80C186EB, TK87C751, and TK68HC711D3 families that have already been requalified at X-Fab. Our TK80C51 is currently being requalified, with an expected release this summer. That qualification will also result in the introduction of TK87C51 programmable versions of the 80C51.
The Tekmos family works hard to design and deliver great "chips" for our customers. In that spirit Tekmos staff get together for a weekly lunch to relax and share stories other than those related to work. February 15th we had a cook out in back of our corporate offices by setting up the Tekmos cabana, bringing tables and office chairs, and setting up the Weber grill to cook burgers, french fries, bratwurst and hot dogs topped with Alan's home made chili. Desert celebrated Alan and Jon's birthdays with a red velvet Nothing Bundt Cake.
|Thank You for Reading Tekmos Talks|
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