|A Newsletter for the Semiconductor Industry|
Welcome to Tekmos Talks May 2017 and 20 Years of Solutions. This month we will share about analog layout, a space parts conference, clock generators, "Inside Tekmos" camp out, and a featured product.
|From the Desk of the President, Lynn Reed|
Analog Layout Approaches
Traditional analog layout uses what is called the full custom approach. Its advantage is that it generates the highest performance analog circuitry. The disadvantage is that it is very labor intensive, and takes a long time to complete. Analog circuitry frequently requires a second revision to adjust parameters. And with a full custom approach, that can mean extensive reworking of the layout, or even starting over.
A second approach is to use pre-existing analog cells. Unfortunately, they may not be optimized for a particular application, and may have to be redone to meet the application requirements.
Another approach is to use an analog array. The array consists of a mixture of transistors, resistors, and capacitors. The circuit is defined by the interconnect, which is typically done in metal or via fabric. Analog arrays generate acceptable performance with greatly reduced layout time and lower NRE charges. On the down side, the circuit is larger than a full custom part, and that adds to the volume production price. One of the main advantages of analog arrays is the savings in time. Not only is the layout time reduced, but frequently wafers can be started before the design is even finished. That is because the analog array contains sufficient flexibility to accommodate design changes to device sizes. Starting the arrays early can cut 4 to 5 weeks off of the wafer processing time. Also, the fab lot can be split, with some wafers held at the programming step, and that will allow a quick turn on the second revision as well.
So what is an analog array? It begins with the need for analog transistors. While all transistors can be considered to be analog, it is frequently necessary in analog design for two adjacent transistors to have matching electrical characteristics. The better the matching, the better the analog performance. In the digital world, the only things that matter are speed and area, so very small transistors are used. But the smallest transistors will have the greatest mismatches, since naturally occurring edge variations are now a greater percentage of the transistor dimensions. These edge effects can be minimized by using larger transistors.
The next decision is to determine what size transistors need to be included in the analog array. In general, there is a need for a number of identical width transistors that can be used as building blocks. There is also a need for a limited number of much wider transistors that can be used as the input stage of op-amps and comparators. And there is a need for longer L devices that can be used in low power applications. There is another need for digital devices that can be used to switch the capacitors used in filters and integrators. But even this is complicated. They can be drawn with equal P and N sizes to minimize switching noise, or they can be drawn with equal strengths for less distortion.
Resistors and Capacitors
An analog array also needs capacitors. In general, you can use a value made up from multiple unit capacitors. But you may also need a few capacitors that are odd sized, for use in scaling capacitor arrays that are used in analog to digital converter arrays.
And we need resistors. Lots of unit resistors, with the unit being typically somewhere between 500 and 1000 ohms. The unit resistors can be combined in series and parallel to produce almost any desired value. There is also a need for larger value resistors. These might be well resistors, or specially implanted poly.
Tiles for Layout
It is convenient to group a select number of transistors, resistors, and capacitors, and group them together in a tile, and then use multiple instances of the tile to create the chip. Unfortunately, you will need more than one type of tile. For example, consider the needs of a band gap voltage reference. The bandgap design needs an array of bipolar transistors in order to work. Bandgaps are almost the only circuit element that needs this array of bipolar devices, and since you can generate multiple voltage references off of a single bandgap, you will likely only need one bandgap per chip. So it would be wasteful to include this bipolar array in every tile. There are several other cases where a specialized tile is a good idea. Even in a specialized tile, the other devices can be generic transistors that are programmed rather than being dedicated to a specific design.
Reducing the Overall Cycle Time
Well before the design is done, the designer will have a very good idea of the amount of circuitry required to complete the design. This makes it possible to combine multiple tiles and digital logic to create a structured array very early in the design process. This array can be started in the fab, and receive the first 5 weeks of processing while the design of the personalization layers is being completed. This can remove an additional month from the overall design cycle, reducing the time to market for the final system.
Give us a call, and learn how Tekmos can help you with your mixed signal applications.
Or fill out the FPGA questionnaire form here.
Or to Request a Quote.
|Space Parts Working Group|
Last month, Tekmos sent a representative to the annual meeting of the Space Parts Working Group. This is a meeting of government users of satellites, companies that make satellites, and component manufacturers that make parts for satellites. The meeting was for two days, and consisted of presentations from government users and the component manufacturers. It also presented a lot of networking opportunities.
Tekmos sells several products into the aerospace market. We are also working on upgrading our quality system from ISO9001 up to AS9100, which is now being required by some of our customers. After that, the next step is changing our products to offer an even higher level of reliability. And the first stage of that process is to determine what are the limits with current parts. And that is why we were at the Space Parts Working Group.
So, what did we learn? Being space related, radiation damage was a big topic. The higher the orbit, the greater the damage. As a subset of radiation, heavy ions are an increasing concern. Heavy ions are also a problem with the aviation market, and have been identified as a cause of commercial aviation engine failure in at least one instance. Another issue was bond wire integrity, as a result of corrosion, thermal cycle, and vibration during launch. And as with all semiconductor users, there were concerns about obsolescence and counterfeiting. These are all areas that will be addressed as we develop the next generation of Tekmos products.
Digital circuits (and some analog circuits as well) frequently need a clock. This is typically provided by either an external clock source, a crystal oscillator, an RC oscillator, or a ceramic resonator. These can be had to any desired level of accuracy. But they all require external components. When space is critical, a self-contained oscillator can be the solution. It is the smallest solution and the low-cost solution. The only problem is accuracy.
A ring oscillator is easy to make, and is quite robust. But the accuracy is bad. The speed will vary with the square of the voltage, the -3/2 power of the temperature, and another +/- 20% with the wafer processing. This can result in 50% tolerances. And you will need around 1% tolerance to make a UART work. So how do you get there? Design is the answer.
Limiting Voltage Sensitivity
We cannot do anything about transistors being sensitive to voltage. But we can limit the voltage swing that the transistors see. So, the solution is to use a bandgap reference to generate a power supply for the ring oscillator. That takes care of one of the variables.
Limiting Process Sensitivity
The process sensitivity is primarily a result of normal variations in the thresholds of P and N transistors. We compensate for this with a trim. But what do we trim, and how do we do it? We have two options for trimming. The first involves adjusting the number of stages in a ring oscillator. This works best when there are a large number of stages. A better method is to adjust the ring oscillator supply voltage up or down to achieve the desired frequency. We use an op-amp to generate the supply voltage from the bandgap. The op-amp is biased with resistors that set the desired voltage. Letting the trim adjust the value of those resistors is an easy way to trim the frequency.
At one time, lasers were used to cut resistors to trim them. That is still an option, but using NVM memory is a preferred solution. We put multiple resistors in the op-amp feedback network, and use transistors to select which resistors to use. The NVM then enables the transistors.
Limiting Temperature Sensitivity
As stated earlier, transistor strengths change as a function of the temperature to the -3/2 power. We can compensate for this temperature change by increasing the ring oscillator supply voltage when temperature increases. This part is challenging, and is beyond the scope of this article. But we would be happy to discuss it in greater detail should you need it in your application.
|Product Feature Corner|
Product Feature:TK80C51FA Microcontroller
The TK80C51FA combines most of the 8051 architecture peripherals into a single chip. It may be used as a pin-for-pin replacement for earlier generations of the 8051 such as the 80C31BH, the 80C32-1, the 80C32X2, and the 80C51FA. This design was created using the Tekmos configurable microprocessor technology, and implemented in our 0.35u CMOS process. The use of the original instruction timing insures that the original code will continue to perform correctly while running in the Tekmos design.
The performance advantages resulting from the 0.35u process allow the Tekmos part to replace all of the earlier version's speed grades. The use of a current process also insures the long term availability of this part.
Tekmos Spring Camp Out
Tekmos held our third camp out in April. We stayed at the Oxford Ranch, which was the same destination as the last two camp outs. The Oxford Ranch is a private campground that offers plenty of room and has decent toilet and shower facilities. The campground is about 70 miles away from Tekmos, and is located near the Enchanted Rock State Park. People have a choice between a day trip, or camping for 1 or 2 days. This time, everyone opted for a 2-day camp out.
One new thing on the camp out was the appearance of a three-level tree house tent. From a "mature" point of view, it looks like it would cause serious back problems, but it does have room for plenty of visitors.
As always, the groups split up on Saturday morning, with those under 30 going off to climb Enchanted Rock, and explore the cave at the top. Those over 30 remain in camp, and keep the coffee pot safe while we solve the world's problems.
We have been improving our camping capabilities with each trip we make. Our main improvements for this trip were a camping coffee pot that works off a stove burner, and a better water supply. Next time we will work on a better kitchen organization and the addition of gourmet food to the menu.
|Thank You for Reading Tekmos Talks|
Thank you for reading Tekmos Talks and helping us celebrate 20 years. Call (512) 342-9871 or email Sales for more information.
Tekmos, 20 years of solutions.
Lynn Reed, President
7901 E. Riverside Dr. Building 2, Suite 150