Specifications
This is the first of a series of articles documenting the design of a dual port, programmable mode, 18K RAM for use in FPGA replacements. Other articles will cover the bit design, word drivers, sense amps, and the timing generator.
The first step in any design process is determining the specifications of what you are to design. In leading edge memory design, the choice is obvious. Take what you did before, multiply the size by 4, and you have your new specifications.
For most custom RAM applications, memory compilers produce a perfectly acceptable result. You specify the memory size, and how wide each word is, the desired speed, the desired process, and run the compiler. You can be done within minutes.
In our case, we need a block RAM whose size can be programmed at personalization, and could even be changed by the user in their application. To get that type of flexibility, we must design our own RAM.
Since our customers will have already been using block RAMs in their FPGA based designs, our research starts with determining what the FPGA providers are doing. What are their block RAM sizes? What modes do they support? Are any of those modes covered by patents? Do I have to include the mode in the RAM design, or can I allow the customer to add that functionality in the form of a wrapper around the RAM built out of logic gates?
Fortunately, the FPGA companies have provided a wealth of technical information about their block RAMs and their operating modes. After reviewing everything, we decided to create a block RAM that looks a lot like the Xilinx 18K block RAM. This article will discuss the design as implemented in our 180nm process. While the core voltage in the 180nm process is nominally 1.8 volts, we have specified our RAM to also work with core voltages of 1.5 and 1.2 volts. We are looking more for functionality than for speed at the lower voltages.
The next article will discuss the bit design.