Libraries for Reverse Engineering

Tekmos is in the business of reverse engineering obsolete designs to support customers who need a continuing supply of these older parts. In these applications, it is necessary to make an identical replacement for the original part.

To make an identical replacement, we image the original part, convert that into a GDS database, and then extract a transistor level schematic. This transistor level schematic is converted into a gate level Verilog netlist, which is then simulated, verified, and eventually turned into an ASIC.

Tekmos already has libraries of gates, latches, and flops. And initially, we just mapped reverse engineered designs using our standard ASIC libraries. But this approach can introduce problems. For example, the Tekmos standard flip flop has reset connected to both the master and slave. In some of the designs that we have reverse engineered, the reset is only connected to the master, and not the slave. Replacing their flop with ours could introduce timing issues that might interfere with the operation of the overall chip.

We reviewed the approach, and decided that the best approach is to create new library cells that are identical to the ones in the original circuit. Or as identical as we can make it.

Some of the latches use cross coupled inverters that require a new value to be forced onto the inverters. This is generally a very bad idea in today’s technology, and there are logical equivalents that will perform the same function with the same timing without having the current spikes. Likewise, we see transmission gates used for logic functions and which can be replaced by more robust gates. But these are the exceptions, and we will create new cells that exactly match the originals for most cases.

Once the library has been created, we must verify it. If there is an error in the library, then it will cause errors in the Verilog simulations, and this can be very difficult to debug. The answer to this problem is to run spice on both the original library and on our implementation, and verify that they both behave in an identical manner. Combinational logic can be verified through a simple binary pattern. Latches and flops require a little more specialized pattern, in which we vary the flop contents with the set and clear controls.

In addition to the simulation library, we must also create a physical library for the place and route software. This is not a difficult task, but is time consuming. To verify this library, we create a dummy chip that contains all the cells, and then place and route it. Then we run DRC and LVS checks to make sure that the transistor level definition of our library matches the physical layout.

And that is how we create a library that provides a good foundation for the rest of the design.