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Tekmos Talks Newsletters

A newsletter for the semiconductor industry

Tekmos Talks 2020

Tekmos Talks December 2020

  

 
Tekmos Talks

A Newsletter for the Semiconductor Industry
December 2020
Welcome to Tekmos Talks. This month Lynn will talk about Old Design Techniques and Wishes for the upcoming Holidays.
From the Desk of the President, Lynn Reed

 

20141210 Lynn 111 
        Lynn Reed, President

 

Old Design Techniques

Tekmos reverse engineers many older circuits. As we do so, we come across interesting ways to implement logical function that are no longer in common use. I thought that we would show some of them here.

Most involve the clever use of a transmission gate. A transmission gate is a basic CMOS switch. It has complimentary enables, and when enabled, allows the input to be connected to the output. The symbol for a transmission gate is shown in Figure 1. There are several things to keep in mind when considering transmission gates. The first is that they are bidirectional. The output is connected to the input through a resistor. This makes a transmission gate very fast, though the presence of the resistance can cause signal attenuation, and ultimately reduces the speed when it drives a large load. The second is that complimentary signals are frequently available in logic design, so they can be used to drive transmission gates without requiring any additional logic.

Figure 1

Designers used these transmission gates to save transistors. The cost of transistors has plummeted and are now basically free. But when they were expensive designers went out of their way to avoid using transistors. The function of a transmission gate depends on the surrounding logic. It can be part of a latch, or of another type of gate. This increases the difficulty to understand how it is being used.

Gate 1

Figure 2 shows a transmission gate with an n-channel transistor on the output. The gate of the transistor is connected to the enable-bar of the transmission gate. When the transmission gate is not enabled (“B”=0), the output is 0. When it is enabled, the output is the “A” input. This makes it a 2-input AND gate. Currently, it takes 6 transistors to make an AND gate. This uses 3 transistors.

Figure 2

Gate 2

Figure 3 shows a similar gate, but with a p-channel transistor on the output. This creates an OR gate with an inverting “B” input. This can save from 3 to 5 transistors, depending on if an inverter was needed to generate the not B signal.

Figure 3

Gates 3, 4, and 5

Two transmission gates can be connected as shown in Figure 4. This can create three different gates, depending on the external signals.

The first gate is a 2:1 mux. “B”=1 selects “A” and “B”=0 selects “C”

The second and third gates occu
r if the “A” and “C” signals are also complimentary. Depending on the choice of whether C = not A or A = not C, the gate in Figure 4 acts as either an Exclusive OR or Exclusive NOR gate.

Figure 4

Gate 6

In this gate, shown in Figure 5, the transmission gate drives two cross-coupled inverters. The transmission gate must be stronger than the inverters, which will allow it to overdrive the inverters, producing a latch.

Figure 5

This concept can be extended as shown in Figure 6 with various combinations of P and N transistors producing sets and resets for the latch. In this case, the sets are Or-ed together, while the resets are AND-ed together. Any group of combinational logic can be created either set or reset the latch, provided that the resulting signal is strong enough to overdrive the inverters.

Figure 6

There are other unusual design techniques, which I will cover in a later newsletter.

 

Thank You for Reading Tekmos Talks

 

Thank you for reading Tekmos Talks and helping us celebrate 20 plus years.

Sincerely,

Lynn Reed, President

 

 
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