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TK28F256 256K CMOS Flash Memory

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  • Non-volatile Flash Memory
    • Data retention with no voltage applied
  • Fast 120 ns Read access time
  • Flash Electrical Chip-Erase
    • 5 Second Typical Chip-Erase
  • Quick Programming Algorithm
    • 10 μs Typical Byte-Program
    • 2 Second Chip-Program
  • 12.0 V ±5% VPP chip erase
  • 100,000 Erase/Program Cycles
  • 10 year data retention
  • CMOS Low Power Consumption
    • 10 mA Typical Active Current
    • 50 μA Typical Standby Current
  • Command Register Architecture for Microprocessor/Microcontroller Compatible Write Interface
  • Great Noise Immunity Features
    • ±10% VCC Tolerance
  • -40ºC to +85ºC operation
  • Safely abort Erase or Program sequence at any time including Integrated Program/Erase Stop Timer
  • Protection against inadvertent programming during power up
  • JEDEC-Standard Pinouts
    • 32-Pin Plastic Dip
    • 32-Lead PLCC
    • 32-Lead TSOP


General Description 

The Tekmos TK28F256 is a high speed 256K CMOS non-volatile flash memory arranged as 32K x 8 (32,768 x 8 bits).  It is electrically erasable and reprogrammable. It is well suited for use in applications where codes are changed after the initial programming, during manufacture, final test or after sale. Memory contents can be changed in a test fixture, in a PROM programmer, or in system. 

The TK28F256 is manufactured to allow for low power consumption and immunity to noise. The device is designed to withstand 100,000 program/erase cycles without losing data integrity. Data retention is at least 10 years. 

Standby current maximum is 100 uA providing significant power saving when the device is deselected. Access time of 90 ns provides zero wait state performance compatible with many microcontrollers and microprocessors. Electrical erasure of the entire memory is typically achieved in less than 5 seconds. 12 volt programming and erase voltage makes it compatible with similar devices. 

The erase procedure has a two-step process that ensures against accidental erasure of the contents of the memory. The erase command is actually written twice before it is executed. An integrated stop feature allows for automatic timing control eliminating the need for a maximum erase timing specification. 

An Abort/Reset command is available to allow the user to safely abort an erase or program sequence. The abort/reset operation can interrupt at any time in a program or erase operation and the device is reset to the Read Mode. 

Protection against inadvertent programming during power up is provided. Vpp and Vcc may be powered up in any order, no sequencing is required. 

The TK28F256 is offered in 32-Pin Plastic DIP or 32-Lead PLCC and 32-Lead TSOP packages. Conforming to JEDEC standards, it is pin for pin compatible with standard EPROM and EEPROM devices. The TK28F256 is often used as a drop in replacement in systems originally designed for other manufacturer’s 28F256 devices.



The data sheet is available here: pdf TK28F256 (326 KB)


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