Unify Chip Card S2


The Tekmos Solution for Your System in a Package

 

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Tekmos provides a fast and low cost solution to integrate customer designs into a small form factor package using its unique low cost die stacking capabilities. There is significant time to market advantages merging various chips into a vertical stack to optimize integration and eliminate large NREs and high risk.  The Tekmos Unify solution includes a design and manufacturing service to handle all engineering from design through production shipment of final tested products.  This service is ideal for companies wishing to integrate their standard ICs to permit more room for other features or special batteries to expand features and extend the operating life of their products. 

Why Unify?

There are applications in which size is critical and non-negotiable.   This could be an ear-bud, a ring, or medical electronics that have to be swallowed.  WLCSP packages are small, but for more complex systems, they may not be small enough.  In these cases, the Tekmos Unify approach of a System in a Package can be the answer.

In the Unify approach, your system ICs are stacked on top of each other, producing a package that is only about 1 mm larger than the largest die, and is only 1 to 1.5 mm thick.

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What types of Devices Can Be Included in Unify?

It the device is available in die form, it can be included in a Unify package.  We can also include resistors, capacitors, crystals, LEDs, accelerometers, and optical detectors.  There are limits that are mostly set by volume.  For example, a big capacitor is not going to fit in a small package.

What Does It Cost?

The base cost is your current bill of materials.  If you use a $4.00 microcontroller, it will still cost $4.00.  To this base cost, we have to add the packaging cost and the testing cost.  And that is going to vary depending both on the number of internal bond wires, and the time necessary to test the completed SiP.

There is usually an NRE charge for the substrate.  And this will vary depending on the number of layers necessary to interconnect your circuit.  There may need to be a package tooling charge if you require molded lenses, pressure holes, or other similar features.  Contact us for details.

Pinout Considerations

Most devices we stack have incompatible pinouts.  One chip may have a data bus that goes from D0 to D7, while another chip has a D7 to D0 order.  This can be resolved by having all chips connect to a common substrate.  This substrate can either be a BGA substrate or it can be a special ASIC.

xrayimageHeight Considerations

We prefer to stack the die in a pyramid configuration.  The height becomes an issue when the stack exceeds 4 die in height.  And sometimes, we may have two pyramids side by side.

Including an ASIC

Sometimes, it makes sense to consolidate some of the components into a mixed signal ASIC.  The ASIC also serves as a substrate, dealing with incompatible pinouts.  And it is a good way to add special interfaces and glue logic.  With over 800 successful ASICs, Tekmos has the experience necessary to support your design.

The ASIC can also contain JTAG circuitry which can assist in the testing of the completed SiP

Testing

Even though we start with Known Good Die (KGD), the completed system must be tested.  Assembly is not a perfect procedure.  Die can break, bond wires can short out, and so the completed SiP must be tested.  Knowing this, Tekmos designs our Unify parts to be tested.  This can be as simple as bringing out key nodes on unused pins, or developing a program for an internal micro that checks out functionality.  

Unify Your Design

Contact us today, and we can start shrinking your design.

Documentation

Tekmos Unify ASICs Program Brochure:  pdf Tekmos Unify ASICs Brochure (2.26 MB)

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